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Are you sure you want to Yes No. Shubhabroto Mukherjee at Delhi Public School. Show More. No Downloads. Views Total views. Actions Shares. No notes for slide. Narasimha Murthy. D yayavaram yahoo. With the developments in VLSI technology, there is a drastic increase in the number of components on a single chip. As a result of increase in the chip density ,the probability of fault occurring also increased.
So,the logic designer must always consider two points. One is ,to confirm whether the digital circuit operates correctly and is free from faults. This involves the process of fault diagnosis and and testing. The second is , correct operation of the circuit is to be ensured even in the presence of faults. This is the process of fault tolerance. There are different types of faults in digital circuits. A Fault in a circuit is defined as the physical defect of one or more components of the circuit.
Faults can be either permanent or temporary. Permanent faults are caused by the breaking or wearing out of components. Permanent faults are also called Hard and Solid faults.
Temporary faults are also known as soft faults are those faults that occur only certain intervals of time. These faults can be either transient or intermittent. A Transient fault is usually caused by some externally induced signal disturbance ,such as power supply fluctuations. An Intermittent fault is one that often occurs when a component is in the process of developing a permanent fault.
Based on the effect of faults ,they are also classified as Logical or Parametric. A logical fault changes the Boolean function realized by the digital circuit ,while a parametric fault alters the magnitude of the circuit parameter causing a change in speed,current or voltage. A very important parametric fault is the delay fault ,which is caused by slow logic gates.
This type of faults leads to problems of Hazards or critical races. The extent of a fault specifies whether the effect of the fault is localized or distributed. A local fault affects only a single variable, whereas a distributed fault affects more than one. A logical fault, for example, is a local fault, whereas the malfunction of the clock is a distributed fault Fault modeling: Logical faults represent the effect of physical faults on the behavior of the modeled system.
The advantage of modeling physical faults as logical faults is firstly fault analysis becomes a 1 2. Second, some logical fault models are technology-independent in the sense that the same fault model is applicable to many technologies. Hence, testing and diagnosis methods developed for such a fault model remain valid despite changes in technology. And third, tests derived for logical faults may be used for physical faults whose effect on circuit behavior is not completely understood or is too complex to be analyzed.
A logical fault model can be explicit or implicit. An explicit fault model defines a fault universe in which every fault is individually identified and hence the faults to be analyzed can be explicitly enumerated. An explicit fault model is practical to the extent that the size of its fault universe is not prohibitively large.
An implicit fault model defines a fault universe by collectively identifying the faults of interest typically by defining their characterizing properties.
So, fault modeling is closely related to the type of modeling used for the system. Faults defined in conjunction with a structural model are referred to as structural faults ; their effect is to modify the interconnections among components. Functional faults are defined in conjunction with a functional model ; for example, the effect of a functional fault maybe to change the truth table of a component or to inhibit an RTL operation. Fault Classes : There are three important classes logical faults.
It assumes that a fault in a logic gate results in one of its inputs or the output is fixed at either a logic 0 stuck-at-0 or at logic 1 stuck-at Stuck-at-0 and stuck-at-l faults are denoted by abbreviations s-a-0 and s-a-1, respectively.
The NAND gate perceives the A input as a logic 1 irrespective of the logic value placed on the input. In the absence of the fault, the output will be 1. The number 1 in the figure below indicates an open, whereas the numbers 2 and 3 denote the short between the output node and the ground and the short between the output node and the VDD, respectively.
A short in a CMOS results if not enough metal is removed by the photolitho graphy , whereas over-removal of metal results in an open circuit.
Fault 1 in figure below will disconnect input A from the gate of transistors T1 and T3. Fault 2 forces the output node to be shorted to VDD, that is, the fault can be considered as an s-a-l fault. Similarly, fault 3 forces the output node to be s-a The stuck-at model is also used to represent multiple faults in circuits.
In a multiple stuck-at fault, it is assumed that more than one signal line in the circuit are stuck at logic 1 or logic 0. A variation of the multiple fault is the unidirectional fault. A multiple fault is unidirectional if all of its constituent faults are either s-a-0 or s-a-l but not both simultaneously.
The stuck-at model is not very effective in accounting for all faults in very large scale integrated VLSI , circuits which mainly uses CMOS technology.
Faults in CMOS circuits do not necessarily produce logical faults that can be described as stuck-at faults. For example, in figure above , faults 3 and 4 create stuck-on transistors faults. Let us consider the figure ii below which implements the Boolean expression In the diagramt , two possible shorts numbered 1 and 2 and two possible opens numbered 3 and 4 are indicated. Short number 1 can be modeled by s-a-1 of input E ; open number 3 can be modeled by s-a-0 of input E, input F, or both.
On the other hand, short number 2 and open number 4 cannot be modeled by any stuck-at fault because they involve a modification of the network function. For example, in the presence of short number 2, the network function will change to the following new function given below.
Without a short, the outputs of gates Z1 and Z2 are whereas with the short, Bridging Faults : Bridging faults are an important class of permanent faults that cannot be modeled as stuck-at faults. A bridging fault is said to have occurred when two or more signal lines in a circuit are connected accidently together.
Bridging faults at the gate level has been classified into three types: input bridging and feedback bridging and non-feedback bridging. An input bridging fault corresponds to the shorting of a certain number of primary input lines. A feedback bridging fault results if there is a short between an output and input line.
A feedback bridging fault may cause a circuit to oscillate, or it may convert it into a sequential circuit. Bridging faults in a transistor-level circuit may occur between the terminals of a transistor or between two or more signal lines. The effect of bridging among the terminals of transistors is technology-dependent. For example, in CMOS circuits, such faults manifest as either stuck-at or stuck-open faults, depending on the physical location and the value of the bridging resistance.
A non-feedback bridging fault identifies a bridging fault that does not belong to either of the above types. From the above it is clear that ,the probability of two lines getting bridged is higher if they are physically close to each other. The theory on the bridging faults assumes that the probability of more than two lines shorting together is very low,and wired logic is performed at the connections. In general a bridging fault in positive logic is assumed to behave as a wired-AND whwere 0 is the dominant logic value and a bridging fault in negative logic behaves as a wired —OR where 1 is the dominant logic value.
Delay Faults : Smaller defects, which are likely to cause partial open or short in a circuit, have a higher probability of occurrence due to the statistical variations in the manufacturing process.
Fault Detection and Diagnosis Algoiitlims for Interconnects. 12 and to devise a formal design for testability (DFT) -strategy for MCM interconnect perfor- rithm for High Throughput MCM Substrate Interconnect Test," poster presentation.
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Select articles Display Method:. Best Papers. Abstract: Testable design techniques for systolic motion estimators based on M-testability conditions are proposed in this paper. The number of test patterns is 2w, where w denotes the word length of a PE. The proposed testable design techniques are also suitable for built-in self-test implementation. According to experimental results, our approaches can achieve To verify our approaches, an experimental chip is also implemented.
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